1. Field
The present application relates to a DC-DC converter and a control method of the DC-DC converter.
2. Description of the Related Art
FIG. 1 illustrates a conventional DC-DC converter 100. The DC-DC converter 100 is a synchronous rectification type DC-DC converter. A high-side transistor FET101 coupled to an input voltage VIN is an N-type field effect transistor (FET). A high level at an output of a driver DRV103 for supplying the high-side transistor FET101 with a gate voltage becomes a value equal to an input voltage Vin plus (+) a power supply voltage VB, based on a boot strap circuit including a capacitor C105 and a diode D106.
As shown in FIG. 1, a first end of the capacitor C105 is coupled to a node LX between a source of the high-side transistor FET101 and a drain of a Low-side transistor FET102, which is coupled to a ground voltage (zero (0) volts). A second end of the capacitor C105 is coupled to a cathode of the diode D106. An anode of the diode D106 is coupled to the power supply voltage VB.
When the conventional DC-DC converter 100 in FIG. 1 operates in a continuous conduction mode (CCM), conduction of the high-side transistor FET101 causes a voltage VLX of the node LX to become a value equal to the input voltage Vin. Then when the low-side transistor FET102 becomes conductive, the voltage VLX of the node LX drops to zero (0) volts from the input voltage VIN. When the voltage VLX of the node LX drops to 0 volts from the input voltage VIN, a potential difference across the capacitor C105 becomes a value equal to the power supply voltage VB.
Next, when the high-side transistor FET101 becomes conductive, the voltage VLX of the node LX rises to the value equal to the input voltage Vin from zero (0) volts. When the voltage VLX rises to the value equal to the input voltage Vin from zero (0) volts, a drive voltage VDVDD of the driver DRV103 becomes equal to the power supply voltage VB plus (+) the input voltage Vin, in response to a capacitive coupling of the capacitor C105.
When the drive voltage VDVDD becomes equal to the power supply voltage VB plus (+) the input voltage Vin, the voltage equal to the power supply voltage VB plus (+) the input voltage Vin is applied to a gate of the high-side transistor FET101. This causes the high-side transistor FET101 to become conductive in low impedance.
FIG. 2 illustrates a timing chart indicating operations of the conventional DC-DC converter 100 in FIG. 1 in a discontinuous conduction mode (DCM).
As shown in FIG. 2, when electromagnetic energy stored in an inductor L of FIG. 1 disappears in the DCM, the voltage VLX of the node LX of FIG. 1 becomes equal to an output voltage Vo in a period 200 in which the high-side transistor FET101 of FIG. 1 and the low-side transistor FET102 of FIG. 1 are non-conductive. When the voltage VLX of the node LX of FIG. 1 becomes equal to the output voltage Vo, the potential difference across the capacitor C105 of FIG. 1 becomes a value equal to the power supply voltage VB minus (−) the output voltage Vo.
When the voltage VLX of the node LX of FIG. 1 becomes equal to the input voltage Vin, the drive voltage VDVDD becomes equal to the power supply voltage VB minus (−) the output voltage Vo plus (+) the input voltage Vin, in response to the capacitive coupling of the capacitor C105 of FIG. 1. When comparing the DCM with the CCM, a voltage lower by the output voltage Vo than that in the case of CCM is supplied to the gate of the high-side transistor FET101 of FIG. 1.
As discussed above, in the conventional DC-DC converter, the voltage that is lower by the output voltage Vo than that in the case of CCM is supplied to the high-side transistor FET101, so that a conductive impedance of the high-side transistor FET101 becomes higher. That is, there arises a problem in that the high-side transistor FET101 becomes non-conductive at the time at which the high-side transistor becomes conductive.